1. Field of the Invention
The present description is related to the field of non volatile memory, and, more specifically, to a non volatile memory with programming through band-to-band tunneling and impact ionization gate current.
2. Description of the Related Art
FIG. 1 shows a prior art circuit design for a non-volatile memory cell. According to the prior art circuit observed in FIG. 1, the amount of charge residing on a floating gate 101 determines whether the cell is storing a logical “1” or a logical “0”. The floating gate 101 is referred to as “floating” because it is not coupled to the typical output end of a transistor (e.g., a source or drain node).
In operation, in order to “program” the memory cell to a first logical state, after turning transistor Q3 “on” from SELECT line 104, high energy electrons are added to the floating gate 101 from transistor Q1. Here, the WELL/SOURCE voltage 102 is set to a voltage that causes a substantial VSD voltage drop from the source to the drain of the Q1 transistor. For instance, according to one approach, the voltage of the WELL/SOURCE node 102 is set to a large positive voltage 2VDD where VDD is a DC supply voltage creating a large voltage drop across transistor Q1. This large voltage drop corresponds to the establishment of a high intensity electric field running from the source of transistor Q1 to the drain of transistor Q1.
Transistor Q1 is also “on” in the sense that the charge level on floating gate 101 corresponds to a floating gate 101 voltage that is sufficiently below VS-VT (where VS is the source voltage of transistor Q1=2VDD and VT is the threshold or “turn-on” voltage of transistor Q1). When transistor Q1 is sufficiently turned “on”, a conductive channel is established within the substrate portion of transistor Q1 just beneath its gate dielectric.
In transporting the current within transistor Q1, holes within transistor Q1's conductive channel flow from Q1's source to drain and, in so doing, are accelerated to very high velocities by the high intensity electric field. These high energy holes collide with the semiconductor substrate lattice from which transistor Q1 is constructed. The collisions with the lattice create high energy electrons that have enough energy to surmount transistor Q1's gate dielectric energy barrier and travel to the floating gate 101 where they are collected. The collection of electrons on the floating gate 101 lowers the charge on the floating gate beneath some threshold which corresponds to a first logical state (e.g., a logical 1 or 0).
In order to “erase” the memory cell to a second logical state, electrons are removed from the floating gate 101 so as to effectively increase the charge on the floating gate 101 beyond a second threshold which corresponds to a second logical state. Here, electrons are tunneled by a Fowler-Nordheim tunneling mechanism from the floating gate 101 into the ERASE node 103 (i.e., the semiconductor substrate portion of transistor Q2). In the case of Fowler-Nordheim tunneling, a large positive voltage is placed on the ERASE node 103 so as to create a strong electric field that runs from the semiconductor substrate portion of transistor Q2 to the floating gate 101. This large positive voltage causes the energy band structure of the gate dielectric of transistor Q2 to resemble a sharp spike which promotes the tunneling of electrons through the energy barrier that resides between the floating gate 101 and the semiconductor substrate portion of transistor Q2.
Thus, the ability to accurately control the logical state being held by the memory cell corresponds to the ability to control the amount of high energy electrons that are injected onto the floating gate 101 from the substrate portion of transistor Q1 during a PROGRAM phase and the ability to accurately control the amount of electrons that tunnel from the floating gate 101 into the substrate portion of transistor Q2 during an ERASE phase. With the ever decreasing size of transistor dimensions (e.g., in terms of gate length and gate dielectric thickness), however, the ability to control these transport mechanisms is proving to be increasingly difficult.
For instance, according to one incorrect realm of operation, “too many” electrons are tunneled into the substrate portion of transistor Q2 during an ERASE phase resulting in the relative charge level of the floating gate 101 rising “too high” (e.g., at or too near VS-VT). In this case, transistor Q1 is not sufficiently “on” and, as a consequence, an insufficient amount of high energy electrons are created and injected onto the floating gate 101. The result is that the first logical state cannot be reached in time.
FIG. 2 depicts the problem graphically. FIG. 2 depicts the flow of high energy electrons onto the floating gate 101 during a PROGRAM phase (referred to as “impact ionization induced injection current”) as a function of the charge that exists on the floating gate 101 (in terms of the difference between the charge level's corresponding floating gate voltage and the source node voltage of transistor Q1 (“normalized |VGS|”)). When the charge level is sufficiently low during the PROGRAM phase, the floating gate 101 voltage is sufficiently below VS-VT which corresponds to region 201 of FIG. 2. The result is a sufficiently large, impact ionization induced injection current onto the floating gate that can reduce the floating gate 101 voltage to the first logical state during the PROGRAM phase.
However, if the charge level on the floating gate rises because too many electrons are tunneled off the floating gate 101 during an ERASE phase, the region of operation for a following PROGRAM phase is to the right of region 201 where a roll-off 202 in the curve is observed. This roll-off 202 corresponds to a drop in the impact ionization induced current that is injected to the floating gate during a PROGRAM phase that results from little or no IDS current flowing through transistor Q1 because of the large floating gate voltage (said another way, transistor Q1 is not sufficiently “on” under such conditions). Thus, if the charge level on the floating gate rises too high from the ERASE phase, region 202 will be reached which corresponds to an impact ionization induced injection current magnitude that is too small to drop the floating gate charge level to the first logical state during the PROGRAM phase.